Semiconductor structure

ABSTRACT

A semiconductor structure includes a substrate, an aluminum nitride layer, plural of grading stress buffer layers and a superlattice structure layer. The aluminum nitride layer is disposed on the substrate. The grading stress buffer layers are disposed on the aluminum nitride layer. Each grading stress buffer layer includes a grading layer and a transition layer stacked up sequentially. A chemical formula of the grading layer is Al 1−x Ga x N, wherein the x value is increased from one side near the substrate to a side away from the substrate, and 0≦x≦1. A chemical formula of the transition layer is the same as the chemical formula of a side surface of the grading layer away from the substrate. The chemical formula of the transition layer of the grading stress buffer layer furthest from the substrate is GaN. The superlattice structure layer is disposed between the aluminum nitride layer and the grading stress buffer layers.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of and claims thepriority benefit of U.S. prior application Ser. No. 13/917,645, filed onJun. 14, 2013, now pending, which claims the priority benefit of Taiwanapplication serial no. 101145835, filed on Dec. 6, 2012. The entirety ofeach of the above-mentioned patent applications is hereby incorporatedby reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor structure. More particularly,the invention relates to a semiconductor structure having grading stressbuffer layers.

2. Description of Related Art

With the progress of semiconductor technologies, a light emitting diode(LED) now has advantages of high luminance, low power consumption,compactness, low driving voltage, being mercury free, and so forth.Therefore, the LED has been extensively applied in the field of displaysand illumination. In general, an LED chip is fabricated by using a broadband-gap semiconductor material, such as gallium nitride (GaN). However,in addition to the difference in thermal expansion coefficient andchemical properties, the difference between the lattice constant of GaNand that of a hetero-substrate cannot be ignored. Hence, due to latticemismatch, GaN grown on the hetero-substrate undergoes latticedislocation, and the lattice dislocation extends toward a thicknessdirection of the GaN layer. Further, because of lattice mismatch betweenGaN and the hetero-substrate, the material of GaN relative to thehetero-substrate will create great structural stress. As the growththickness becomes thicker, the stress accumulated becomes greater. Whenexceeding a threshold value, the material layer will be unable tosupport the stress, and must deform to release the stress. As such, thelattice dislocation not only causes crystal growth defects which reducethe light emitting efficiency of the LED and shortens lifetime, it alsocan not grow very thick GaN.

SUMMARY OF THE INVENTION

The invention is directed to a semiconductor structure, capable ofreleasing the stress problem caused by conventional lattice mismatch,and reducing lattice dislocation from extending in a thicknessdirection.

The invention provides a semiconductor structure, including a siliconsubstrate, an aluminum nitride layer, and a plurality of grading stressbuffer layers. The aluminum nitride layer is disposed on the siliconsubstrate. The grading stress buffer layers are disposed on the aluminumnitride layer. Each grading stress buffer layer includes a grading layerand a transition layer stacked up sequentially. A chemical formula ofthe grading layer is Al_(1−x)Ga_(x)N, wherein the x value is increasedfrom one side near the silicon substrate to a side away from the siliconsubstrate, and 0≦x≦1. A chemical formula of the transition layer is thesame as the chemical formula of a side surface of the grading layer awayfrom the silicon substrate. The chemical formula of the transition layerof the grading stress buffer layer furthest away from the siliconsubstrate is GaN.

In an embodiment of the invention, the thickness of the grading layer ofthe grading stress buffer layers increase from a side close to thesilicon substrate to a side away from the silicon substrate.

In an embodiment of the invention, the thickness of each grading layerranges from 50 nm to 700 nm.

In an embodiment of the invention, the thickness of the transition layerof the grading stress buffer layers increase from a side close to thesilicon substrate to a side away from the silicon substrate.

In an embodiment of the invention, the thickness of each transitionlayer ranges from 50 nm to 700 nm.

In an embodiment of the invention, the x value of the chemical formulaof the transition layer increases as an arithmetic progression.

In an embodiment of the invention, the grading stress buffer layersinclude 2 to 10 grading stress buffer layers.

In an embodiment of the invention, the semiconductor structure furtherincludes a superlattice structure layer, disposed between the aluminumnitride layer and the plurality of grading stress buffer layers. Thesuperlattice structure layer includes a plurality of aluminum galliumindium nitride structure layers. Each aluminum gallium indium nitridestructure layer includes a first aluminum gallium indium nitride layerand a second aluminum gallium indium nitride layer stacked on eachother. The chemical formula of the first aluminum gallium indium nitridelayers is Al_(s)Ga_(t)In_((1−x−t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1.The chemical formula of the second aluminum gallium indium nitridelayers is Al_(m)Ga_(n)In_((1−m−n))N, wherein 0<m<1, 0<n<1, and 0<m+n≦1.When m=s, n≠t, and when n=t, m≠s.

In an embodiment of the invention, the thickness of each aluminumgallium indium nitride structure layer ranges from 5 nm to 500 nm.

In an embodiment of the invention, the thickness of the superlatticestructure layer ranges from 20 nm to 5000 nm.

In an embodiment of the invention, the superlattice structure layerincludes 5 or more aluminum gallium indium nitride structure layers.

In an embodiment of the invention, the semiconductor structure furtherincludes a superlattice structure layer, disposed between the pluralityof grading stress buffer layers. The superlattice structure layerincludes a plurality of aluminum gallium indium nitride structurelayers. Each aluminum gallium indium nitride structure layer includes afirst aluminum gallium indium nitride layer and a second aluminumgallium indium nitride layer stacked on each other. The chemical formulaof the first aluminum gallium indium nitride layers isAl_(s)Ga_(t)In_((1−s−t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1. Thechemical formula of the second aluminum gallium indium nitride layers isAl_(m)Ga_(n)In_((1−m−n))N, wherein 0<m<1, 0<n<1, and 0<m+n≦1. When m=s,n≠t, and when n=t, m≠s.

In an embodiment of the invention, the thickness of each aluminumgallium indium nitride structure layer ranges from 5 nm to 500 nm.

In an embodiment of the invention, the thickness of the superlatticestructure layer ranges from 20 nm to 5000 nm.

In an embodiment of the invention, the superlattice structure layerincludes 5 or more aluminum gallium indium nitride structure layers.

Based on the above, since a plurality of grading stress buffer layersare disposed on the aluminum nitride layer of the invention, the amountof gallium can be increased, so as to achieve a GaN layer. As such, thestress generated from the lattice difference between the GaN layer andthe silicon substrate can be effectively reduced. In addition, latticedislocation extending in a thickness direction can also be effectivelyreduced, improving the overall quality of the semiconductor structure.

Several exemplary embodiments accompanied with figures are described indetail below to further describe the invention in details.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the disclosure, and are incorporated in and constitutea part of this specification. The drawings illustrate embodiments of thedisclosure and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic cross-sectional view of a semiconductor structureaccording to an embodiment of the invention.

FIG. 2 is a schematic cross-sectional view of a semiconductor structureaccording to another embodiment of the invention.

FIG. 3 is a schematic cross-sectional view of a semiconductor structureaccording to yet another embodiment of the invention.

DESCRIPTION OF EMBODIMENTS

In the description of the following embodiments, when a layer (or film)or a structure is disposed “above” or “below” another substrate, anotherlayer (or film), or another structure, it should be understood that thelayer (or film) or the structure can be “directly” located on anothersubstrate, layer (or film), or another structure. Or, the two layers (orfilms) or structures can have one or more middle layers so as to be“indirectly” disposed on each other. The Examiner can refer to theattached figures for the position of each layer.

FIG. 1 is a schematic cross-sectional view of a semiconductor structureaccording to an embodiment of the invention. Referring to FIG. 1, in theembodiment, a semiconductor structure 100 a includes a silicon substrate110, an aluminum nitride layer 120, and a plurality of grading stressbuffer layers 140 a, 140 b, 140 c, and 140 d (FIG. 1 only shows four).The silicon substrate 110 has an upper surface 112. The aluminum nitridelayer 120 is disposed on the upper surface 112 of the silicon substrate110. The grading stress buffer layers 140 a, 140 b, 140 c, and 140 d aredisposed on the aluminum nitride layer 120. Each grading stress bufferlayer 140 a (or 140 b, 140 c, 140 d) includes a grading layer 142 a (or142 b, 142 c, 142 d) and a transition layer 144 a (or 144 b, 144 c, 144d) stacked up sequentially. A chemical formula of the grading layers 142a, 142 b, 142 c, 142 d is Al_(1−x)Ga_(x)N, wherein the x value isincreased from one side near the upper surface 112 of the siliconsubstrate 110 to a side away from the upper surface 112 of the siliconsubstrate 110, and 0≦x≦1. Each transition layer 144 a (or 144 b, 144 c,144 d) and a side surface 1422 a (or 1422 b, 1422 c, 1422 d) of eachgrading layer 142 a (or 142 b, 142 c, 142 d) furthest away from thesilicon substrate is made up of the same elements.

For example, the x value of the chemical formula of the grading layer142 a of the grading stress buffer layer 140 a is, for example, between0 and 0.25. That is to say, the Al amount of the grading layer 142 adecreases from a side close to the aluminum nitride layer 120 to a sideaway from the aluminum nitride layer 120 (i.e. the Al amount decreasesfrom 1 to 0.75). The Ga amount increases from a side close to thealuminum nitride layer 120 to a side away from the aluminum nitridelayer 120 (i.e. the Ga amount increases from 0 to 0.25). The transitionlayer 144 a and the side surface 1422 a of the grading layer 142 afurthest from the silicon substrate 110 are made up of the same elements(i.e. the chemical formula of the transition layer 144 a isAl_(0.75)Ga_(0.25)N).

Similarly, the x value of the chemical formula of the grading layer 142b of the grading stress buffer layer 140 b is, for example, between 0.25and 0.5. That is to say, the Al amount of the grading layer 142 bdecreases from a side close to the aluminum nitride layer 120 to a sideaway from the aluminum nitride layer 120 (i.e. the Al amount decreasesfrom 0.75 to 0.5). The Ga amount increases from a side close to thealuminum nitride layer 120 to a side away from the aluminum nitridelayer 120 (i.e. the Ga amount increases from 0.25 to 0.5). Thetransition layer 144 b and the side surface 1422 b of the grading layer142 b furthest from the silicon substrate are made up of the sameelements (i.e. the chemical formula of the transition layer 144 b isAl_(0.5)Ga_(0.5)N).

The x value of the chemical formula of the grading layer 142 c of thegrading stress buffer layer 140 c is, for example, between 0.5 and 0.75.That is to say, the Al amount of the grading layer 142 c decreases froma side close to the aluminum nitride layer 120 to a side away from thealuminum nitride layer 120 (i.e. the Al amount decreases from 0.5 to0.25). The Ga amount increases from a side close to the aluminum nitridelayer 120 to a side away from the aluminum nitride layer 120 (i.e. theGa amount increases from 0.5 to 0.75). The transition layer 144 c andthe side surface 1422 c of the grading layer 142 c furthest from thesilicon substrate are made up of the same elements (i.e. the chemicalformula of the transition layer 144 c is Al_(0.25)Ga_(0.75)N).

The x value of the chemical formula of the grading layer 142 d of thegrading stress buffer layer 140 d is, for example, between 0.75 and 1.That is to say, the Al amount of the grading layer 142 d decreases froma side close to the aluminum nitride layer 120 to a side away from thealuminum nitride layer 120 (i.e. the Al amount decreases from 0.25 to0). The Ga amount increases from a side close to the aluminum nitridelayer 120 to a side away from the aluminum nitride layer 120 (i.e. theGa amount increases from 0.75 to 1). Specifically, the transition layer144 d of the grading stress buffer layer 140 d furthest from the siliconsubstrate 110 and the side surface 1422 d of the grading layer 142 dfurthest from the silicon substrate are made up of the same elements(i.e. the chemical formula of the last transition layer 144 d is GaN).

That is to say, the x value (i.e. the gallium amount) of the chemicalformula of the transition layers 144 a, 144 b, 144 c, 144 d of thegrading stress buffer layers 140 a, 140 b, 140 c, 140 d increases as anarithmetic progression, and the aluminum amount decreases with aproportional arithmetic progression. Of course, in other embodiments,the x value of the chemical formula of the transition layers 144 a, 144b, 144 c, 144 d can increase without an arithmetic progression, and isnot limited thereto.

Furthermore, the thicknesses h1, h2, h3, h4 of the grading layers 142 a,142 b, 142 c, 142 d of the grading stress buffer layers 140 a, 140 b,140 c, 140 d increase from close to an upper surface 112 of the siliconsubstrate 110 to away from the upper surface 112 of the siliconsubstrate 110. That is to say, the thickness h1 of the grading layer 142a is less than the thickness h2 of the grading layer 142 b. Thethickness h2 of the grading layer 142 b is less than the thickness h3 ofthe grading layer 142 c. The thickness h3 of the grading layer 142 c isless than the thickness h4 of the grading layer 142 d. Herein,preferably, the thickness h1 (or h2, h3, h4) of each grading layer 142 a(or 142 b, 142 c, 142 d) ranges between 50 nm and 700 nm. It should benoted that with the thicknesses of the grading layers falling withinthis range, the growth quality is more stable and will be less likely tohave defects.

In addition, the thicknesses of the transition layers 144 a, 144 b, 144c, 144 d of the grading stress buffer layers 140 a, 140 b, 140 c, 140 dincrease from close to an upper surface 112 of the silicon substrate 110to away from the upper surface 112 of the silicon substrate 110. That isto say, the thickness h1′ of the transition layer 144 a is less than thethickness h2′ of the transition layer 144 b. The thickness h2′ of thetransition layer 144 b is less than the thickness h3′ of the transitionlayer 144 c. The thickness h3′ of the transition layer 144 c is lessthan the thickness h4′ of the transition layer 144 d. Herein,preferably, the thickness h1′ (or h2′, h3′, h4′) of each transitionlayer 144 a (or 144 b, 144 c, 144 d) ranges between 50 nm and 700 nm. Itshould be noted that with the thicknesses of the transition layersfalling within this range, the growth quality is more stable and will beless likely to have defects.

In the semiconductor structure 100 a of the embodiment, the gradingstress buffer layers 140 a, 140 b, 140 c, 140 d are disposed on thealuminum nitride layer 120. The aluminum amount in the transition layers144 a, 144 b, 144 c, 144 d decreases as an arithmetic progression, andthe gallium amount increases as an arithmetic progression. Thetransition layer 144 a, 144 b, 144 c, 144 d and the side surface 1422 a(or 1422 b, 1422 c, 1422 d) of the grading layer 142 a, 142 b, 142 c,142 d furthest from the silicon substrate 110 are made up of the samealuminum amount and gallium amount. Thus, a GaN layer can be obtained(i.e. transition layer 144 d). The grading stress buffer layers 140 a,140 b, 140 c, 140 d can be used to reduce the stress caused by theexpansion coefficient and the lattice difference between the GaN layer(i.e. the transition layer 144 d) and the silicon substrate 110. Besidesthe grading stress buffer layers 140 a, 140 b, 140 c, 140 d having thefunction of relieving stress, conventional lattice dislocation extendingin a thickness direction can also be reduced, improving the overallquality of the semiconductor structure 100 a.

Of course, the number of the grading stress buffer layers 140 a, 140 b,140 c, 140 d shown are exemplary. One skilled in the art can adjust theamount of aluminum and gallium and increase the number of grading stressbuffer layers. If the x value (i.e. the gallium amount) increases by anarithmetic progression of 0.1, the number of grading stress bufferlayers can be 10. This way, the stress caused by the expansioncoefficient and the lattice difference between the GaN layer (i.e. thetransition layer 144 d) and the silicon substrate 110 can be reduced;details are not repeated herein.

It is noted that the following embodiment uses the same referencenumerals and partial content of the previous embodiment. The samereference numerals represent similar components, and repeateddescription is omitted. Those not described in the following embodimentcan be referred to in the above embodiment.

FIG. 2 is a schematic cross-sectional view of a semiconductor structureaccording to another embodiment of the invention. Referring to FIG. 2,the semiconductor structure 100 b of the embodiment is similar to thesemiconductor structure 100 a of FIG. 1. The difference between the twois that the semiconductor structure 100 b of the embodiment furtherincludes a superlattice structure layer 150 a. The superlatticestructure layer 150 a is disposed between the aluminum nitride layer 120and the grading stress buffer layers 140 a, 140 b, 140 c, 140 d.

In detail, the superlattice structure layer 150 a is disposed betweenthe aluminum nitride layer 120 and the grading stress buffer layer 140a. The super lattice structure layer 150 a includes a plurality ofaluminum gallium indium nitride structure layers 152 a 1, 152 a 2 (FIG.2 only shows two). Each aluminum gallium indium nitride structure layer152 a 1 (or 152 a 2) includes a first aluminum gallium indium nitridelayer 151 a 1 (or 151 a 2) and a second aluminum gallium indium nitridelayer 153 a 1 (or 153 a 2) stacked on each other. The chemical formulaof the first aluminum gallium indium nitride layers 151 a 1, 151 a 2 isAl_(s)Ga_(t)In_((1−s−t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1. Thechemical formula of the second aluminum gallium indium nitride layers153 a 1, 153 a 2 is Al_(m)Ga_(n)In_(1−s−t))N, wherein 0<m<1, 0<n<1, and0<m+n≦1. When m=s, n≠t, and when n=t, m≠s. That is to say, the ratio ofthe elements of the first aluminum gallium indium nitride layer 151 a 1(or 151 a 2) and the second aluminum gallium indium nitride layer 153 a1 (or 153 a 2) are not exactly the same.

For example, the chemical formula of the first aluminum gallium indiumnitride layer 151 a 1 of the aluminum gallium indium nitride structurelayer 152 a 1 is Al_(0.3)Ga_(0.2)In_(0.5)N, and the chemical formula ofthe second aluminum gallium indium nitride layer 153 a 1 isAl_(0.3)Ga_(0.4)In_(0.3)N. In addition, the thickness t1, t2 of eachaluminum gallium indium nitride structure layer 152 a 1, 152 a 2 ranges,for example, from 5 nm to 500 nm. The thickness t of the superlatticestructure 150 a, for example, ranges from 20 nm to 5000 nm. Preferably,the number of aluminum gallium indium nitride structure layers 152 a 1,152 a 2 is at least five. Because the superlattice structure 150 a isdisposed between the aluminum nitride layer 120 and the grading stressbuffer layer 140 a, the design can help in reducing the stress caused bythe expansion coefficient and the lattice difference between the gradingstress buffer layer 140 a and the silicon substrate 110. In addition,the dislocation framed before the superlattice structure 150 a is growncan be prevented, so that the dislocation is unable to continue to grow.This further improves the quality of the semiconductor structure 100 b.

FIG. 3 is a schematic cross-sectional view of a semiconductor structureaccording to yet another embodiment of the invention. Referring to FIG.3, the semiconductor structure 100 c of the embodiment is similar to thesemiconductor structure 100 a of FIG. 1. The difference between the twois that the semiconductor structure 100 c of the embodiment furtherincludes a superlattice structure layer 150 b. The superlatticestructure layer 150 b is disposed between the grading stress bufferlayer 140 a and the grading stress buffer layer 140 b. The superlatticestructure layer 150 b includes a plurality of aluminum gallium indiumnitride structure layers 152 b 1, 152 b 2. Each aluminum gallium indiumnitride structure layer 152 b 1 (or 152 b 2) includes a first aluminumgallium indium nitride layer 151 b 1 (or 151 b 2) and a second aluminumgallium indium nitride layer 153 b 1 (or 153 b 2) stacked on each other.The chemical formula of the first aluminum gallium indium nitride layers151 b 1, 151 b 2 is Al_(s)Ga_(t)In_((1−s−t))N, wherein 0<s<1, 0<t<1, and0<s+t≦1. The chemical formula of the second aluminum gallium indiumnitride layers 153 b 1, 153 b 2 is Al_(m)Ga_(n)In_((1−m−n))N, wherein0<m<1, 0<n<1, and 0<m+n≦1. When m=s, n≠t, and when n=t, m≠s. That is tosay, the ratio of the elements of the first aluminum gallium indiumnitride layer 151 b 1 (or 151 b 2) and the second aluminum galliumindium nitride layer 153 b 1 (or 153 b 2) are not exactly the same.

For example, the chemical formula of the first aluminum gallium indiumnitride layer 151 b 1 of the aluminum gallium indium nitride structurelayer 152 b 1 is Al_(0.3)Ga_(0.2)In_(0.5)N, and the chemical formula ofthe second aluminum gallium indium nitride layer 153 b 1 isAl_(0.3)Ga_(0.4)In_(0.3)N. In addition, the thickness t1′, t2′ of eachaluminum gallium indium nitride structure layer 152 b 1, 152 b 2 ranges,for example, from 5 nm to 500 nm. The thickness t′ of the superlatticestructure 150 b, for example, ranges from 20 nm to 5000 nm. Preferably,the number of aluminum gallium indium nitride structure layers 152 b 1,152 b 2 is at least five. Because the superlattice structure 150 a isdisposed between the adjacent grading stress buffer layers 140 a, 140 b,the design can help in reducing the stress caused by the expansioncoefficient and the lattice difference between the grading stress bufferlayers 140 a, 140 b. In addition, the dislocation foamed before thesuperlattice structure 150 b is grown can be prevented, so that thedislocation is unable to continue to grow. This further improves thequality of the semiconductor structure 100 c.

It should be noted that the invention does not limit the position andtype of the superlattice structures 150 a, 150 b even though thesuperlattice structures 150 a, 150 b have been to described to belocated between the aluminum nitride layer 120 and the grading stressbuffer layer 140 a, or, between the grading stress buffer layer 140 aand the grading stress buffer layer 140 b. In other embodiments notshown, the superlattice structure can be disposed between any twoneighboring layers of the grading stress buffer layers 140 a, 140 b, 140c, 140 d; for example, between the grading layer 142 a and thetransition layer 144 a, or the grading layer 142 c and the transitionlayer 144 c. Or, the superlattice structures can at the same time bedisposed between the aluminum nitride layer 120 and the grading stressbuffer layer 140 a, and between any two neighboring layers of thegrading stress buffer layers 140 a, 140 b, 140 c, 140 d. One skilled inthe art can adjust or increase the design of the superlattice structuresaccordingly, so as to satisfy reducing of dislocation. This is still apart of the technical proposal of the invention and does not depart fromthe protection scope of the invention.

To sum up, since a plurality of grading stress buffer layers aredisposed on the aluminum nitride layer of the invention, the amount ofgallium can be increased, so as to achieve a GaN layer. Therefore, thestress generated from the lattice difference between the GaN layer andthe silicon substrate can be effectively reduced. In addition, latticedislocation extending in a thickness direction can also be effectivelyreduced, improving the overall quality of the semiconductor structure.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of thedisclosed embodiments without departing from the scope or spirit of theinvention. In view of the foregoing, it is intended that the disclosurecover modifications and variations of this specification provided theyfall within the scope of the following claims and their equivalents.

What is claimed is:
 1. A semiconductor structure, comprising: asubstrate; an aluminum nitride layer disposed on the substrate; aplurality of grading stress buffer layers disposed on the aluminumnitride layer, wherein each of the grading stress buffer layers includesa grading layer and a transition layer stacked up sequentially, achemical formula of each of the grading layers is Al_(1−x)Ga_(x)N,wherein an x value is increased from a side of any grading layer nearthe substrate to a side of any grading layer away from the substrate,and 0≦x≦1, wherein a chemical formula of each of the transition layersis the same as a chemical formula of a side surface furthest away fromthe substrate of each of the corresponding grading layers, and achemical formula of the transition layer of the grading stress bufferlayer furthest away from the substrate is GaN, wherein each of the aplurality of grading stress buffer layers disposed on the aluminumnitride layer, wherein each of the grading stress buffer layers includesa bottom surface near the substrate and a top surface opposite to thebottom surface, a chemical formula of each of the grading stress bufferlayers is Al_(1−x)Ga_(x)N, the x value of all the grading stress bufferlayers varies continuously from 0 to 1 along a direction from thebottommost bottom surface to the uppermost top surface, wherein each ofthe grading stress buffer layers comprises a grading layer and atransition layer stacked up sequentially along the direction, the xvalue of the grading layers increase continuously along the direction,the x value of the transition layers is constant, and a chemical formulaof the uppermost transition layer is GaN; and a superlattice structurelayer, disposed between the aluminum nitride layer and the plurality ofgrading stress buffer layers, wherein the superlattice structure layerincludes a plurality of aluminum gallium indium nitride structurelayers, each of the aluminum gallium indium nitride structure layersincludes a first aluminum gallium indium nitride layer and a secondaluminum gallium indium nitride layer stacked on each other, a chemicalformula of the first aluminum gallium indium nitride layers isAl_(s)Ga_(t)In_((1−s−t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1, and achemical formula of the second aluminum gallium indium nitride layers isAl_(m)Ga_(n)In_((1−m−n))N, wherein 0<m<1, 0<n<1, and 0<m+n≦1, and whenm=s, n≠t, and when n=t, m≠s.
 2. The semiconductor structure as claimedin claim 1, wherein a thickness of each of the aluminum gallium indiumnitride structure layers is between 5 nm and 500 nm.
 3. Thesemiconductor structure as claimed in claim 2, wherein the thickness ofthe superlattice structure layer is between 20 nm and 5000 nm.
 4. Thesemiconductor structure as claimed in claim 1, wherein the superlatticestructure layer includes 5 or more aluminum gallium indium nitridestructure layers.
 5. A semiconductor structure, comprising: a substrate;an aluminum nitride layer disposed on the substrate; a plurality ofgrading stress buffer layers disposed on the aluminum nitride layer,wherein each of the grading stress buffer layers includes a gradinglayer and a transition layer stacked up sequentially, a chemical formulaof each of the grading layers is Al_(1−x)Ga_(x)N, wherein an x value isincreased from a side of any grading layer near the substrate to a sideof any grading layer away from the substrate, and 0≦x≦1, wherein achemical formula of each of the transition layers is the same as achemical formula of a side surface furthest away from the substrate ofeach of the corresponding grading layers, and a chemical formula of thetransition layer of the grading stress buffer layer furthest away fromthe substrate is GaN, wherein each of the a plurality of grading stressbuffer layers disposed on the aluminum nitride layer, wherein each ofthe grading stress buffer layers includes a bottom surface near thesubstrate and a top surface opposite to the bottom surface, a chemicalformula of each of the grading stress buffer layers is Al_(1−x)Ga_(x)N,the x value of all the grading stress buffer layers varies continuouslyfrom 0 to 1 along a direction from the bottommost bottom surface to theuppermost top surface, wherein each of the grading stress buffer layerscomprises a grading layer and a transition layer stacked up sequentiallyalong the direction, the x value of the grading layers increasecontinuously along the direction, the x value of the transition layersis constant, and a chemical formula of the uppermost transition layer isGaN; and a superlattice structure layer, disposed between the pluralityof grading stress buffer layers, wherein the superlattice structurelayer includes a plurality of aluminum gallium indium nitride structurelayers, each of the aluminum gallium indium nitride structure layersincludes a first aluminum gallium indium nitride layer and a secondaluminum gallium indium nitride layer stacked on each other, a chemicalformula of the first aluminum gallium indium nitride layers isAl_(s)Ga_(t)In_((1−s−t))N, wherein 0<s<1, 0<t<1, and 0<s+t≦1, and achemical formula of the second aluminum gallium indium nitride layers isAl_(m)Ga_(n)In_((1−m−m))N, wherein 0<m<1, 0<n<1, and 0<m+n≦1, and whenm=s, n≠t, and when n=t, m≠s.
 6. The semiconductor structure as claimedin claim 5, wherein a thickness of each of the aluminum gallium indiumnitride structure layers is between 5 nm and 500 nm.
 7. Thesemiconductor structure as claimed in claim 6, wherein the thickness ofthe superlattice structure layer is between 20 nm and 5000 nm.
 8. Thesemiconductor structure as claimed in claim 5, wherein the superlatticestructure layer includes 5 or more aluminum gallium indium nitridestructure layers.